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si8239x data sheet 4.0 a isodrivers with 2.5 v vddi and safety features the si8239x combines two isolated drivers with either an independent input control or a single input into a single package for high power applications. all drivers operate with a 2.5 v input vdd and a maximum drive supply voltage of 24 v. the si8239x isolators are ideal for driving power mosfets and igbts used in a wide variety of switched power and motor control applications. these drivers utilize silicon laboratories' proprietary silicon isolation technology, supporting up to 5 kvrms with- stand voltage. this technology enables high cmti (100 kv/s), lower prop delays and skew, reduced variation with temperature and age and tighter part-to-part matching. it also offers some unique features such as an output uvlo fault detection and feed- back, and automatic shutdown for both drivers, an en (active high) instead of a dis (ac- tive low) pin, a safe delayed start-up time of 1 ms, fail-safe drivers with default low in case of vddi power-down, and dead time programmability. the si8239x family offers longer service life and dramatically higher reliability compared to opto-coupled gate driv- ers. applications ? power delivery systems ? motor control systems ? isolated dc-dc power supplies ? lighting control systems ? solar and industrial inverters safety approvals (pending) ? ul 1577 recognized ? up to 5000 vrms for 1 minute ? csa component notice 5a approval ? iec 60950-1 ? vde certification conformity ? vde 0884-10 ? en 60950-1 (reinforced insulation) ? cqc certification approval ? gb4943.1 key features ? two isolated drivers in one package ? up to 5 kvrms isolation ? up to 1500 vdc peak driver-to-driver differential voltage ? enhanced output uvlo safety ? status feedback to controller ? both outputs drive low on uvlo ? en pin for enhanced safety ? extended vddi: 2.5 v C 5.5 v ? pwm and dual driver versions ? 4.0 a peak output ? high electromagnetic immunity ? extended start-up time (1ms) for safe initialization sequence ? 30 ns propagation delay ? transient immunity: 100 kv/s ? programmable dead time ? 10C200 ns ? 40C400 ns ? deglitch option for filtering noise ? wide operating range ? C40 to +125 c ? rohs-compliant packages ? soic-16 wide body ? soic-16 narrow body ? aec-q100 qualified silabs.com | smart. connected. energy-friendly. rev. 0.9
1. ordering guide table 1.1. si8239x ordering guide ordering part number configuration output uvlo enhanced uvlo uvlo status pin delayed startup time dead-time setting deglitch package type isolation rating available now si82390ad-is dual, via, vib 6 v yes yes yes n/a no soic-16 wb 5 kvrms si82390bd-is dual, via, vib 8 v yes yes yes n/a no soic-16 wb 5 kvrms si82390cd-is dual, via, vib 12 v yes yes yes n/a no soic-16 wb 5 kvrms si82395ad-is dual, via, vib 6 v no yes yes n/a no soic-16 wb 5 kvrms si82395bd-is dual, via, vib 8 v no yes yes n/a no soic-16 wb 5 kvrms si82395cd-is dual, via, vib 12 v no yes yes n/a no soic-16 wb 5 kvrms si82397ad-is dual, via, vib 6 v no no yes n/a no soic-16 wb 5 kvrms SI82397BD-IS dual, via, vib 8 v no no yes n/a no soic-16 wb 5 kvrms si82397cd-is dual, via, vib 12 v no no yes n/a no soic-16 wb 5 kvrms si82391ad-is dual, via, vib 6 v yes yes no n/a no soic-16 wb 5 kvrms si82391bd-is dual, via, vib 8 v yes yes no n/a no soic-16 wb 5 kvrms si82391cd-is dual, via, vib 12 v yes yes no n/a no soic-16 wb 5 kvrms si82396ad-is dual, via, vib 6 v no yes no n/a no soic-16 wb 5 kvrms si82396bd-is dual, via, vib 8 v no yes no n/a no soic-16 wb 5 kvrms si82396cd-is dual, via, vib 12 v no yes no n/a no soic-16 wb 5 kvrms si82394ad-is hs/ls, pwm 6 v no yes yes 10C200 ns no soic-16 wb 5 kvrms si82394bd-is hs/ls, pwm 8 v no yes yes 10C200 ns no soic-16 wb 5 kvrms si82394cd-is hs/ls, pwm 12 v no yes yes 10C200 ns no soic-16 wb 5 kvrms si82398ad-is hs/ls, pwm 6 v no yes no 10C200 ns no soic-16 wb 5 kvrms si82398bd-is hs/ls, pwm 8 v no yes no 10C200 ns no soic-16 wb 5 kvrms si82398cd-is hs/ls, pwm 12 v no yes no 10C200 ns no soic-16 wb 5 kvrms contact silicon labs to order the following product options si82390ab-is1 dual, via, vib 6 v yes yes yes n/a no soic-16 nb 2.5 kvrms si82390bb-is1 dual, via, vib 8 v yes yes yes n/a no soic-16 nb 2.5 kvrms si82390cb-is1 dual, via, vib 12 v yes yes yes n/a no soic-16 nb 2.5 kvrms si82395ab-is1 dual, via, vib 6 v no yes yes n/a no soic-16 nb 2.5 kvrms si82395bb-is1 dual, via, vib 8 v no yes yes n/a no soic-16 nb 2.5 kvrms si82395cb-is1 dual, via, vib 12 v no yes yes n/a no soic-16 nb 2.5 kvrms si8239x data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 0.9 | 1
ordering part number configuration output uvlo enhanced uvlo uvlo status pin delayed startup time dead-time setting deglitch package type isolation rating si82394ab4-is1 hs/ls, pwm 6 v no yes yes 40C400 ns yes soic-16 nb 2.5 kvrms si82394bb4-is1 hs/ls, pwm 8 v no yes yes 40C400 ns yes soic-16 nb 2.5 kvrms si82394cb4-is1 hs/ls, pwm 12 v no yes yes 40C400 ns yes soic-16 nb 2.5 kvrms si82394ad4-is hs/ls, pwm 6 v no yes yes 40C400 ns yes soic-16 wb 5 kvrms si82394bd4-is hs/ls, pwm 8 v no yes yes 40C400 ns yes soic-16 wb 5 kvrms si82394cd4-is hs/ls, pwm 12 v no yes yes 40C400 ns yes soic-16 wb 5 kvrms si82391ab-is1 dual, via, vib 6 v yes yes no n/a no soic-16 nb 2.5 kvrms si82391bb-is1 dual, via, vib 8 v yes yes no n/a no soic-16 nb 2.5 kvrms si82391cb-is1 dual, via, vib 12 v yes yes no n/a no soic-16 nb 2.5 kvrms si82396ab-is1 dual, via, vib 6 v no yes no n/a no soic-16 nb 2.5 kvrms si82396bb-is1 dual, via, vib 8 v no yes no n/a no soic-16 nb 2.5 kvrms si82396cb-is1 dual, via, vib 12 v no yes no n/a no soic-16 nb 2.5 kvrms si82398ab4-is1 hs/ls, pwm 6 v no yes no 40C400 ns yes soic-16 nb 2.5 kvrms si82398bb4-is1 hs/ls, pwm 8 v no yes no 40C400 ns yes soic-16 nb 2.5 kvrms si82398cb4-is1 hs/ls, pwm 12 v no yes no 40C400 ns yes soic-16 nb 2.5 kvrms si82398ad4-is hs/ls, pwm 6 v no yes no 40C400 ns yes soic-16 wb 5 kvrms si82398bd4-is hs/ls, pwm 8 v no yes no 40C400 ns yes soic-16 wb 5 kvrms si82398cd4-is hs/ls, pwm 12 v no yes no 40C400 ns yes soic-16 wb 5 kvrms note: 1. all products are rated at 4 a output drive current max, vddi = 2.5 v C 5.5 v, en (active high) 2. all packages are rohs-compliant with peak reflow temperatures of 260 c according to the jedec industry standard classifica- tions and peak solder temperatures. 3. si and si are used interchangeably. si8239x data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 0.9 | 2
2. system overview the operation of an si8239x channel is analogous to that of an optocoupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si8239x channel is shown in the following figure. figure 2.1. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. see the following figure for more details. figure 2.2. modulation scheme si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 3
2.1 typical performance characteristics (4.0 amp) the typical performance characteristics depicted in the following figures are for information purposes only. refer to the electrical char- acteristics table for actual specification limits. figure 2.3. rise/fall time vs. supply voltage figure 2.4. propagation delay vs. supply voltage figure 2.5. rise/fall time vs. load figure 2.6. propagation delay vs. load figure 2.7. propagation delay vs. temperature figure 2.8. supply current vs. supply voltage figure 2.9. supply current vs. supply voltage figure 2.10. supply current vs. temperature si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 4
figure 2.11. output sink current vs. supply voltage figure 2.12. output source current vs. supply voltage figure 2.13. output sink current vs. temperature figure 2.14. output source current vs. temperature 2.2 family overview and logic operation during startup the si8239x family of isolated drivers consists of high-side/low-side and dual driver configurations. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 5
2.2.1 device behavior the following are truth tables for the si8239x families. table 2.1. si82390/1 dual drivers enhanced uvlo and status via vib en 1 vddi vdda vddb voa vob rdy notes h l h p 2 p p h l h l h h p p p l h h h h h p p p h h h l l h p p p l l h x x l/nc p p p l l h device disabled x x x up 2 p p l l ud 3 fail-safe output when vddi unpowered x x h p p up l ud l voa, vob are actively driven low if either vdda or vddb is up x x h p up p ud l l note: 1. the en pin needs to be pulled down with a 100 k resistor externally to gnd. 2. the chip can be powered through the via,vib input esd diodes even if vddi is unpowered. it is recommended that inputs be left unpowered when vddi is unpowered. the en pin has a special esd circuit that prevents the ic from powering up through the en pin. 3. ud = undetermined if same side power is up. table 2.2. si82395/6 dual drivers with uvlo status via vib en 1 vddi vdda vddb voa vob rdy notes h l h p p p h l h l h h p p p l h h h h h p p p h h h l l h p p p l l h x x l/nc p p p l l h device disabled x x x up 2 p p l l ud 3 fail-safe output when vddi unpowered h x h p p up h ud l voa depends on vdda state l x h p p up l ud l x h h p up p ud h l vob depends on vddb state x l h p up p ud l l note: 1. the en pin needs to be pulled down with a 100 k resistor externally to gnd. 2. the chip can be powered through the via,vib input esd diodes even if vddi is unpowered. it is recommended that inputs be left unpowered when vddi is unpowered. the en pin has a special esd circuit that prevents the ic from powering up through the en pin. 3. ud = undetermined if same side power is up. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 6
table 2.3. si82397 dual drivers with no uvlo status via vib en 1 vddi vdda vddb voa vob notes h l h p p p h l l h h p p p l h h h h p p p h h l l h p p p l l x x l/nc p p p l l device disabled x x x up 2 p p l l fail-safe output when vddi is unpowered h x h p p up h ud 3 voa depends on vdda state l x h p p up l ud x h h p up p ud h vob depends on vddb state x l h p up p ud l note: 1. the en pin needs to be pulled down with a 100 k resistor externally to gnd. 2. the chip can be powered through the via,vib input esd diodes even if vddi is unpowered. it is recommended that inputs be left unpowered when vddi is unpowered. the en pin has a special esd circuit that prevents the ic from powering up through the en pin. 3. ud = undetermined if same side power is up. table 2.4. si82394/8 pwm input hs/ls drivers with uvlo status pwm en 1 vddi vdda vddb voa vob rdy notes h h p p p h l h see dead-time note and figure 2.18 dead time waveforms for high- side/low-side drivers on page 12 for timing l h p p p l h h x l/nc p p p l l h device disabled x x up 2 p p l l ud 3 fail-safe output when vddi unpowered h h p p up h ud l voa depends on vdda state l h p p up l ud l h h p up p ud l l vob depends on vddb state l h p up p ud h l note: 1. the en pin needs to be pulled down with a 100 k resistor externally to gnd. 2. the chip can be powered through the pwm input esd diodes even if vddi is unpowered. it is recommended that inputs be left unpowered when vddi is unpowered. the en pin has a special esd circuit that prevents the ic from powering up through the en pin. 3. ud = undetermined if same side power is up. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 7
2.3 power supply connections isolation requirements mandate individual supplies for vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pins of the si8239x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 2.4 power dissipation considerations proper system design must assure that the si8239x operates within safe thermal limits across the entire load range. the si8239x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. equation 1 shows si8239x power dissipation. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 8
substituting values for pdmax tjmax, ta, and ja into equation 2 results in a maximum allowable total power dissipation of 1.19 w. maximum allowable load is found by substituting this limit and the appropriate data sheet values from table 4.1 electrical characteris- tics 1,2 on page 15 into equation 1 and simplifying. the result is equation 3 (4.0 a driver), which assumes vddi = 5 v and vdda = vddb = 18 v. equation 3 is graphed in the following figure where the points along the load line represent the package dissipation-limited value of c l for the corresponding switching frequency. figure 2.15. max load vs. switching frequency 2.5 layout considerations it is most important to minimize ringing in the drive path and noise on the si8239x vdd lines. care must be taken to minimize parasitic inductance in these paths by locating the si8239x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and vdd planes for power devices and small signal components provides the best overall noise performance. 2.6 undervoltage lockout operation device behavior during start-up, normal operation and shutdown is shown in figure 2.16 si82391/6/8 device behavior during normal operation and shutdown on page 10 , where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power supply (vddi) is not present. 2.6.1 device startup outputs voa and vob are held low during power-up until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 9
2.6.2 undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own undervoltage lockout monitors. the si8239x input side enters uvlo when vddi < vddiuvC, and exits uvlo when vddi > vddiuv+. the driver outputs, voa and vob, remain low when the input side of the si8239x is in uvlo and their respective vdd supply (vdda, vddb) is within tolerance. each driver output can enter or exit uvlo independently for the si82394/5/6/7/8 products. for example, voa unconditionally enters uvlo when vdda falls below vddauvC and exits uvlo when vdda rises above vddauv+. for the si82390/1 products, when ei- ther vdda or vddb falls under vddxuvC, this information is fed back through the isolation barrier to the input side logic which forces vob or voa to be driven low respectively under these conditions. if the application is driving a transformer for an isolated power con- verter, for example, this behavior is useful to prevent flux imbalances in the transformer. please note that this feature implies that it can only be implemented when the vdda and vddb power supplies are independent from each other. if a bootstrap circuit is used for si82390/1, it will prevent the ic from powering up. please do not use the si82390/1 in conjunction with a bootstrap circuit for driver power. figure 2.16. si82391/6/8 device behavior during normal operation and shutdown si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 10
figure 2.17. si82390/4/5/7 device behavior during normal operation and shutdown 2.6.3 control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm input versions (si82394/8), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 2.6.4 enable input when brought low, the en input unconditionally drives voa and vob low regardless of the states of via and vib. device operation terminates within tsd after en = vil and resumes within trestart after en = vih. the en input has no effect if vddi is below its uvlo level (i.e., voa, vob remain low). the en pin should be connected to gndi through a 100 k pull-down resistor. 2.6.5 delayed startup time product options si82390/4/5/7 have a safe startup time (tstartup_safe) of 1ms typical from input power valid to output showing valid data. this feature allows users to proceed through a safe initialization sequence with a monotonic output behavior. 2.6.6 rdy pin this is a digital output pin available on all options except the si82397. the rdy pin is h if all the uvlo circuits monitoring vddi, vdda, and vddb are above uvlo threshold. it indicates that device is ready for operation. an l status indicates that one of the power supplies (vddi, vdda, or vddb) is in an unpowered state. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 11
2.7 programmable dead time and overlap protection all high-side/low-side drivers (si82394/8) include programmable dead time, which adds a user-programmable delay between transitions of voa and vob. when enabled, dead time is present on all transitions. the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per the equation below. note that the dead time pin should be connected to gnd1 through a resistor between the values of 6 k and 100 k and a filter capacitor of 100 pf in parallel as shown in figure 3.1 si82394/8 in half-bridge application on page 13 . it is highly recommended it not be tied to vddi. see figure 2.18 dead time waveforms for high-side/low-side drivers on page 12 below. figure 2.18. dead time waveforms for high-side/low-side drivers 2.8 de-glitch feature a de-glitch feature is provided on some options, as defined in the ordering guide. the de-glitch basically provides an internal time de- lay during which any noise is ignored and will not pass through the ic. it is about 30 ns; so, for these product options, the prop delay will be extended by 30 ns. si8239x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 0.9 | 12
3. applications the following examples illustrate typical circuit configurations using the si8239x. 3.1 high-side/low-side driver the following figure shows the si82394/8 controlled by a single pwm signal. figure 3.1. si82394/8 in half-bridge application in the above figure, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. vob is connected as a conventional low-side driver. note that the input side of the si8239x re- quires vddi in the range of 2.5 to 5.5 v, while the vdda and vddb output side supplies must be between 6.5 and 24 v with respect to their respective grounds. the boot-strap start up time will depend on the cb cap chosen. also note that the bypass capacitors on the si8239x should be located as close to the chip as possible. si8239x data sheet applications silabs.com | smart. connected. energy-friendly. rev. 0.9 | 13
3.2 dual driver the following figure shows the si82390/1/5/6/7 configured as a dual driver. note that the drain voltages of q1 and q2 can be refer- enced to a common ground or to different grounds with as much as 1500 vdc between them. figure 3.2. si82390/1/5/6/7 in a dual driver application because each output driver resides on its own die, the relative voltage polarities of voa and vob can reverse without damaging the driver. a dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes. si8239x data sheet applications silabs.com | smart. connected. energy-friendly. rev. 0.9 | 14
4. electrical characteristics table 4.1. electrical characteristics 1,2 parameter symbol test condition min typ max unit dc specifications input-side power supply voltage vddi 2.5 3.3 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb 6.5 24 v input supply quiescent current en = 0 iddi(q) si82390/1/4/5/6/8 2.8 3.8 ma si82397 1.5 2.1 ma output supply quiescent current, per channel en = 0 idda(q), iddb(q) si82390/1/4/5/6/8 4.2 6.5 ma si82397 1.5 2.5 ma input supply active current iddi si82390/1/5/6 via, vib freq = 1 mhz 5.0 7.2 ma si82394/8: pwm freq = 1 mhz 5.2 7.3 si82397: via, vib freq = 1 mhz 3.7 5.6 output supply active current, per channel idda/b si82390/1/4/5/6/8: input freq = 1 mhz, no load 7.1 16.0 ma si82397: input freq = 1 mhz, no load 4.4 12.4 input pin leakage current, via, vib, pwm ivia, ivib, ipwm C10 +10 a input pin leakage current, en ienable C10 +10 a logic high input threshold vih ttl levels 2.0 v logic low input threshold vil ttl levels 0.8 v input hysteresis vi hyst 400 450 mv logic high output voltage voah, vobh ioa, iob = C1 ma vdda, vddb C 0.04 v logic low output voltage voal, vobl ioa, iob = 1 ma 0.04 v output short-circuit pulsed source current ioa(scl), iob(scl) see figure 4.1 iol sink cur- rent test on page 18 4.0 a output short-circuit pulsed source current ioa(sch), iob(sch) see figure 4.2 ioh source current test on page 18 2.0 a output sink resistance r on(sink) 1.0 output source resistance r on(source) 2.7 vddi undervoltage threshold vddi uv+ vddi rising 2.15 2.3 2.5 v vddi undervoltage threshold vddi uvC vddi falling 2.1 2.2 2.4 v vddi lockout hysteresis vddi hys 80 100 mv si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 15
parameter symbol test condition min typ max unit vdda, vddb undervoltage threshold vdda uv+ , vddb uv+ vdda, vddb rising v 6 v 5.0 6.0 7.0 8 v 7.2 8.6 10.0 12 v 9.2 11.1 12.8 vdda, vddb undervoltage threshold vdda uvC , vddb uvC vdda, vddb falling v 6 v 4.7 5.8 6.7 8 v 6.6 8.0 9.3 12 v 8.7 10.1 11.6 vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo = 6 v uvlo = 8 v uvlo = 12 v 200 450 600 280 600 1000 mv uvlo fault shutdown time enhanced mode si82390/1 only vdda uvC to vob low vddb uvC to voa low 120 ns uvlo fault shutdown time vdda uvC to voa low vddb uvC to vob low 500 ns uvlo fault to rdy t_flt 92 ns ac specifications minimum pulse width 30 ns propagation delay t phl , t plh si82390/1/5/6/7 20 30 40 ns vdda/b = 12 v t phl si82394/8 20 30 40 ns c l = 0 pf t plh si82394/8 (measured with 6 k rdt resistor; includes minimum dead time.) 35 45 55 ns pulse width distortion |t plh C t phl | pwd vdda/b = 12 v c l = 0 pf 2.7 5.60 ns programmed dead time for product options with 10C200 ns dead time set- ting range dt rdt = 6 k rdt = 15 k rdt = 100 k 9 23 150 14 33 200 19 43 250 ns output rise and fall time t r ,t f c l = 200 pf 12 ns shutdown time from enable false t sd 60 ns restart time from enable true t restart 60 ns device start-up time input time from vddi_ = vddi_uv + to voa, vob = via, vib si82390/4/5/7 t start_safe 1 ms si82391/6/8 t start 40 s si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 16
parameter symbol test condition min typ max unit device start-up time output t start_out time from vdda/b = vdda/ b_uv+ to voa, vob = via, vib 60 s common mode transient immunity cmti via, vib, pwm = vddi or 0 v v cm = 1500 v 35 100 kv/s note: 1. 2.5 v < vddi < 5.5 v; 6.5 v < vdda, vddb < 24 v; t a = C40 to +125 c. 2. typical specs at 25 c, vdda = vddb = 12 v for 5 v and 8 v uvlo devices, otherwise 15 v. si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 17
the following figures depict sink current, source current, and common-mode transient immunity test circuits, respectively. figure 4.1. iol sink current test figure 4.2. ioh source current test si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 18
figure 4.3. cmti test circuit table 4.2. regulatory information 1,2,3 csa the si8239x is certified under csa component acceptance notice 5a. for more details, see file 232873. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. vde the si8239x is certified according to vde 0884-10. for more details, see file 5006301-4880-0001. vde 0884-10: up to 891 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. ul the si8239x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si8239x is certified under gb4943.1-2011. for more details, see certificates cqcxxx (tbd). rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. note: 1. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. 2. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. 3. for more information, see ordering guide. si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 19
table 4.3. insulation and safety-related specifications parameter symbol test condition value unit wbsoic-16 nbsoic-16 nominal air gap (clearance) 1 l(1o1) 8.0 4.01 mm nominal external tracking (creepage) l(1o2) 8.0 4.01 mm minimum internal gap (internal clear- ance) 0.014 0.014 mm tracking resistance (proof tracking in- dex) pti iec60112 600 600 v erosion depth ed 0.019 0.019 mm resistance (input- output) 2 r io 10 12 10 12 capacitance (input- output) 2 c io f = 1 mhz 1.4 1.4 pf input capacitance 3 c i 4.0 4.0 pf note: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in 7. package outline: 16-pin wide body soic and 9. package outline: 16-pin narrow body soic . vde certifies the clearance and creepage limits as 4.7 mm mini- mum for the nb soic-16 and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for component level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb so- ic16 and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si8239x is converted into a 2-terminal device. pins 1C8 are shorted together to form the first terminal,and pins 9C16 are shorted together to form the second terminal. the parameters are then measured be- tween these two terminals. 3. measured from input pin to ground. table 4.4. iec 60664-1 (vde 0884) ratings parameter test condition specification wb soic-16 nb soic-16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iv i-iii rated mains voltages < 400 v rms i-iii i-ii rated mains voltages < 600 v rms i-iii i-ii si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 20
table 4.5. iec 60747-5-5 insulation characteristics parameter symbol test condition characteristic unit wb soic-16 nb soic-16 maximum working insulation voltage v iorm 891 560 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial dis- charge < 5 pc) 1671 1050 v peak transient overvolt- age v iotm t = 60 sec 6000 4000 v peak pollution degree (din vde 0110, see table 4.1 electrical characteristics 1,2 on page 15 ) 2 2 insulation resist- ance at t s , v io = 500 v r s >10 9 >10 9 note: 1. maintenance of the safety data is ensured by protective circuits. the si8239x provides a climate classification of 40/125/21. table 4.6. iec safety limiting values 1 parameter symbol test condition wb soic-16 nb soic-16 unit case temperature t s 150 150 c safety input current i s ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16) v ddi = 5.5 v, v dda = v ddb = 24 v, t j = 150 c, t a = 25 c 50 50 ma device power dissi- pation 2 p d 1.2 1.2 w note: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figure 4.4 wb soic-16, nb soic-16 thermal derating curve, dependence of safety limiting values with case temperature per vde 0884-10 on page 23 . 2. the si8239x is tested with vddi = 5.5 v, vdda = vddb = 24 v, tj = 150 oc, cl = 100 pf, input 2 mhz 50% duty cycle square wave. si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 21
table 4.7. thermal characteristics parameter symbol wb soic-16 nb soic-16 unit ic junction-to-air ther- mal resistance ja 100 105 c/w table 4.8. absolute maximum ratings 1 parameter symbol min max unit ambient temperature under bias t a C40 +125 c storage temperature t stg C65 +150 c junction temperature t j +150 c input-side supply volt- age vddi C0.6 6.0 v driver-side supply volt- age vdda, vddb C0.6 30 v voltage on any pin with respect to ground v io C0.5 vdd + 0.5 v peak output current (t pw = 10 s, duty cycle = 0.2%) i opk 4.0 a lead solder tempera- ture (10 s) 260 c esd per aec-q100 hbm 4 kv cdm 2 kv maximum isolation (input to output) (1 s) wb so- ic-16 6500 v rms maximum isolation (out- put to output) (1 s) wb soic-16 2500 v rms maximum isolation (input to output) (1 s) nb so- ic-16 4500 v rms maximum isolation (out- put to output) (1 s) nb soic-16 2500 v rms note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 22
figure 4.4. wb soic-16, nb soic-16 thermal derating curve, dependence of safety limiting values with case temperature per vde 0884-10 si8239x data sheet electrical characteristics silabs.com | smart. connected. energy-friendly. rev. 0.9 | 23
5. top-level block diagrams figure 5.1. si82390/1 dual isolated drivers with enhanced uvlo safety si8239x data sheet top-level block diagrams silabs.com | smart. connected. energy-friendly. rev. 0.9 | 24
figure 5.2. si82394/98 single-input high-side/low-side isolated drivers si8239x data sheet top-level block diagrams silabs.com | smart. connected. energy-friendly. rev. 0.9 | 25
figure 5.3. si82395/96 dual isolated drivers with rdy pin si8239x data sheet top-level block diagrams silabs.com | smart. connected. energy-friendly. rev. 0.9 | 26
figure 5.4. si82397 dual isolated drivers si8239x data sheet top-level block diagrams silabs.com | smart. connected. energy-friendly. rev. 0.9 | 27
6. pin descriptions figure 6.1. si8239x soic-16 table 6.1. pin descriptions pin name description gndi input-side ground terminal. via non-inverting logic input terminal for driver a. vib non-inverting logic input terminal for driver b. vddi input-side power supply terminal; connect to a source of 2.5 to 5.5 v. en device enable. when low or nc, this input unconditionally drives outputs voa, vob low. when high, device is ena- bled to perform in normal operating mode. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. nc no connection. gndb ground terminal for driver b. vob driver b output (low-side driver). vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. gnda ground terminal for driver a. voa driver a output (high-side driver). vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. rdy power ready on secondary side for driver a and driver b (both uvlo thresholds for vdda and vddb need to be crossed). high state indicates uvlo thresholds crossed, low state indicates uvlo low condition. no reset is necessary. si8239x data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 0.9 | 28
7. package outline: 16-pin wide body soic the following figure illustrates the package details for the si8239x in a 16-pin wide body soic. the table lists the values for the dimen- sions shown in the illustration. figure 7.1. 16-pin wide body soic table 7.1. package diagram dimensions symbol millimeters min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 si8239x data sheet package outline: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 0.9 | 29
symbol millimeters min max h 0.25 0.75 0 8 aaa 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020c specification for small body, lead-free components. si8239x data sheet package outline: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 0.9 | 30
8. land pattern: 16-pin wide body soic the following figure illustrates the recommended land pattern details for the si8239x in a 16-pin wide-body soic. the table lists the values for the dimensions shown in the illustration. figure 8.1. 16-pin wide body soic pcb land pattern table 8.1. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 note: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protru- sion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si8239x data sheet land pattern: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 0.9 | 31
9. package outline: 16-pin narrow body soic the following figure illustrates the package details for the si8239x in a 16-pin narrow-body soic. the table lists the values for the dimensions shown in the illustration. figure 9.1. 16-pin narrow body soic table 9.1. package diagram dimensions dimension min max dimension min max a 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 h 0.25 0.50 b 0.31 0.51 0 8 c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si8239x data sheet package outline: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 0.9 | 32
10. land pattern: 16-pin narrow body soic the following figure illustrates the recommended land pattern details for the si8239x in a 16-pin narrow-body soic. the table lists the values for the dimensions shown in the illustration. figure 10.1. 16-pin narrow body soic pcb land pattern table 10.1. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 note: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si8239x data sheet land pattern: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 0.9 | 33
11. top markings 11.1 si8239x top marking (16-pin wide body soic) 11.2 top marking explanation (16-pin wide body soic) line 1 marking: base part number ordering options see ordering guide for more informa- tion. si8239 = isodriver product series y = output configuration: 0, 1, 4, 5, 6, 7, 8 0, 1, 5, 6, 7 = dual drivers 4, 8 = pwm input high side/low side drivers u = uvlo level: a, b, c a = 6 v; b = 8 v; c = 12 v v = isolation rating: b, d b = 2.5 kv; d = 5.0 kv d = dead time setting range: none, 4 none = 10C200 ns; 4 = 40C400 ns line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) e4 pb-free symbol country of origin iso code abbreviation tw = taiwan si8239x data sheet top markings silabs.com | smart. connected. energy-friendly. rev. 0.9 | 34
11.3 si8239x top marking (16-pin narrow body soic) 11.4 top marking explanation (16-pin narrow body soic) line 1 marking: base part number ordering options see ordering guide for more informa- tion. si8239 = isodriver product series y = output configuration: 0, 1, 4, 5, 6, 7, 8 0, 1, 5, 6, 7 = dual drivers 4, 8 = pwm input high side/low side drivers u = uvlo level: a, b, c a = 6 v; b = 8 v; c = 12 v v = isolation rating: b, d b = 2.5 kv; d = 5.0 kv d = dead time setting range: none, 4 none = 10C200; 4 = 40C400 line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. si8239x data sheet top markings silabs.com | smart. connected. energy-friendly. rev. 0.9 | 35
table of contents 1. ordering guide .............................. 1 2. system overview .............................. 3 2.1 typical performance characteristics (4.0 amp) ................... 4 2.2 family overview and logic operation during startup ................ 5 2.2.1 device behavior ............................ 6 2.3 power supply connections ......................... 8 2.4 power dissipation considerations ....................... 8 2.5 layout considerations ........................... 9 2.6 undervoltage lockout operation ....................... 9 2.6.1 device startup ............................. 9 2.6.2 undervoltage lockout .......................... 10 2.6.3 control inputs ............................. 11 2.6.4 enable input .............................. 11 2.6.5 delayed startup time .......................... 11 2.6.6 rdy pin ............................... 11 2.7 programmable dead time and overlap protection ................. 12 2.8 de-glitch feature ............................. 12 3. applications ............................... 13 3.1 high-side/low-side driver ......................... 13 3.2 dual driver ............................... 14 4. electrical characteristics .......................... 15 5. top-level block diagrams ......................... 24 6. pin descriptions ............................. 28 7. package outline: 16-pin wide body soic .................... 29 8. land pattern: 16-pin wide body soic ..................... 31 9. package outline: 16-pin narrow body soic ................... 32 10. land pattern: 16-pin narrow body soic .................... 33 11. top markings .............................. 34 11.1 si8239x top marking (16-pin wide body soic) .................. 34 11.2 top marking explanation (16-pin wide body soic) ................. 34 11.3 si8239x top marking (16-pin narrow body soic) ................. 35 11.4 top marking explanation (16-pin narrow body soic) ................ 35 table of contents 36
disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com

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